As semiconductor devices are scaled down to dimensions smaller than 0.25 .mu.m, it is necessary to reduce the polysilicon gate thickness in order to maintain a vertical aspect ratio around one and to reduce the minimum spacing between polysilicon features. However, reducing the thickness of the polysilicon for forming transistor gates for sub 0.25 .mu.m CMOS processes has proven to be extremely difficult.
Conventional CMOS processes for technologies down to 0.25 .mu.m typically deposit 2000 .ANG. of polysilicon followed by an ion implantation and an anneal. The polysilicon is then patterned and etched to form the transistor gates. However, reducing the polysilicon thickness for sub 0.25 .mu.m technologies requires a reduction of the ion implant energy in order to prevent the penetration of dopants into the channel region. In addition, when implanting a thin polysilicon layer with a high dose of dopants, outdiffusion of the same dopants may occur during the subsequent anneal step. An alternative solution to reducing the polysilicon gate thickness may be the use of insitu-doped polysilicon. However, the complexity of such processing renders it extremely difficult to implement.
Thus, there is a need for a simple method for reducing the thickness of the polysilicon transistor gates for sub 0.25 micron processes which does not require a reduction in the ion implant energy, which does not cause outdiffusion, and which facilitates dual doping of the polysilicon to form the transistor gates.